1. Field of the Invention
The present invention relates to a transmission method, transmission circuit and transmission system, in particular to a transmission method, transmission circuit and transmission system for transmitting data between semiconductor chips inside a semiconductor device including a plurality of semiconductor chips.
2. Description of the Related Art
Recently, the integration density of a semiconductor circuit has been improved thanks to miniaturization of semiconductor integrated circuits, and this trend has developed central processing units (CPU) into high-performance devices and memories into high-capacity devices. However, there is a limit to miniaturization of semiconductor integrated circuits. Accordingly, it is necessary to introduce a new technology in order to further increase the integration density. As one technology, a semiconductor device including stacked semiconductor chips has been proposed. For example, see Japanese Patent Application Laid-open H04-196263 and Japanese Patent Application Laid-open 2002-26283. Japanese Patent Application Laid-open H04-196263 discloses a means for realizing a large scale integrated circuit in which its chip area is not changed by stacking semiconductors. Japanese Patent Application Laid-open H04-196263 also discloses a technique for integrating a memory circuit in a separate chip that is stacked over the main semiconductor integrated circuit. On the other hand, Japanese Patent Application Laid-open 2002-26283 discloses a further increased capacity multi-layered memory structure by constructing memory cell arrays in multi-levels.
FIG. 1 shows a schematic sectional diagram showing one example of a chip stacked semiconductor device. When semiconductor chips 120 are arranged in layers, in addition to interconnections within each chip surface, interconnections between chips are needed. Through-hole interconnection 121 is used as the interconnection between chips. Through-hole interconnection 121 is a wiring that penetrates from the top surface to the undersurface of a semiconductor substrate of a chip in order to improve interconnection density. Here, reference numeral 122 denotes an insulation film. Non-patent document 1 (K. Takahashi et al., Japanese Journal of Applied Physics, 40, 3032(2001)) discloses a technique for forming through-hole interconnection. Specifically, first, a Si substrate that is to be the semiconductor chip is thinned down to 50 μm. Then, a hole of 10 μm square that penetrates from the top surface through to the undersurface of the substrate is formed in the substrate. Subsequently, the hole is filled up with metal so as to form a through-hole interconnection for inter-chip wiring. If this through-hole interconnection is used as an inter-chip wiring, it becomes possible to arrange inter-chip wiring three-dimensionally within the chip surface, and it also becomes possible to provide some hundreds of inter-chip lines. Between such multi-layered semiconductor chips, data is transmitted via through-hole interconnections.
FIG. 2 is a configurational diagram showing one example of a transmission circuit for performing data transmission between semiconductor chips. This transmission circuit transmits 1-bit (binary) digital data via through-hole interconnection 15 between transmission-side chip 10 and reception-side chip 20. FIG. 3 is a waveform chart when two bits of data are transmitted in parallel in the transmission circuit shown in FIG. 2.
In the transmission circuit of FIG. 2, the data transmitted from flip-flop 11 in transmission-side chip 10 at the leading edge timing of the inter-chip synchronizing clock is sent to the outside of transmission-side chip 10 by way of output buffer 12. FIG. 3(A) shows inter-chip synchronizing clock CLK. Transmission-side chip 10, using both Data0 as 1-bit (binary) data shown in FIG. 3(B), and Data1 as 1-bit (binary) data shown in FIG. 3(C), transmits data having a value “1” during the first clock cycle of inter-chip synchronizing clock CLK, data having a value “2” during the second cycle, data having a value “0” during the third cycle and data having a value “3” during the fourth cycle. Here, in order to transmit two bits of data in parallel, two circuit portions each consisting of flip-flop 11 and output buffer 12 are needed. Similarly, reception-side chip 20 also needs two circuit portions having the configuration shown in FIG. 2.
The data transmitted from transmission-side chip 10 is received by reception-side chip 20 via through-hole interconnection 15. Reception-side chip 20 includes ESD protecting element 21 at the input terminal. In reception-side chip 20, the received data is supplied to the data input terminal of flip-flop 23 via input buffer 22. Flip-flop 23 takes up the received data supplied to the data input terminal at the leading edge timing of the clock supplied to the clock input terminal of flip-flop 23. FIGS. 3(D) and 3(E) show received 1-bit (binary) data Data0 and 1-bit(binary) data Data1, taken up by flip-flop 23 in reception-side chip 20. The clock in transmission-side chip 10 and the clock in reception-side chip 20 are synchronized with each other.
In the transmission circuit shown in FIG. 2 for transmitting binary digital data of “0” and “1”, the parasite capacitance of through-hole interconnection 15 and the capacitance of ESD protecting element 21 in reception-side chip 20 are charged and discharged based on the transmission data. Among four transmission data transition patterns, specifically, the transition pattern from “1” to “1”, the transition pattern from “1” to “0”, the transition pattern from “0” to “0” and the transition pattern from “0” to “1”, discharging is done in the transition pattern from “1” to “0” while charging is done in the transition pattern from “0” to “1”. Accordingly, when charging or discharging is done once, the number of times of charging/discharging is defined as 1, and the number of times of charging/discharging to transmit 1-bit data is expected to be 0.5 time for each clock cycle on average.
Since, when signal transmission between chips is done using through-hole interconnection 15 in the aforementioned transmission circuit, both the parasite capacitance of through-hole interconnection 15 and the capacitance of ESD protecting element 21 need to be charged and discharged, there is a problem that a large amount of electric power will be consumed. This problem will be detailed hereinbelow. The through-hole interconnection, differing from interconnections that have a 1 μm thickness in the chip plane, needs to have a thickness of 10 μm or greater. This is because in order to position the through-hole electrodes formed in individual semiconductor chips using different processes, the through-hole interconnection needs to have a size one digit greater than several a μm that is used as the positioning accuracy between chips.
Since the through-hole interconnection has a large thickness, its parasite capacitance that is made with the substrate is greater than that of the interconnection within the chip surface. For example, a through-hole interconnection that has a round section that is 20 μm in diameter with an insulation film that has a thickness of 250 nm formed around the outer periphery and that is formed passing through a Si semiconductor substrate, has an interconnection capacitance of 0.45 pF when the substrate is 50 μm thick or when the length of the through-hole wire is 50 μm. The interconnection capacitance of the wire on the surface generally used in the chip surface is about 0.2 pF per 1 mm length. Accordingly, the parasite capacitance on the through-hole interconnection per unit length is 45 times greater than the parasite capacitance of the in-plane interconnection. Further, in the case of inter-chip transmission, it is also necessary to attach an ESD protecting element to the signal input terminal of the chip. This also adds capacitance. As a result, when signal transmission between chips is carried out using through-hole interconnection 15, a large amount of electric power is consumed to charge and discharge the capacitance.
In inter-chip transmission, which entails a power consumption problem when through-hole interconnection is used, in order to reduce the electric power for charging and discharging for inter-chip transmission, it is necessary to transmit the same amount of data as the amount of data that is to be transmitted in binary form, by a lower number of times of charging/discharging than the number of times of charging/discharging that occurs during the transmission of the data in binary form. In other words, it is necessary to send a greater amount of data by the same number of times of charging/discharging. For example, there is a method of transmitting a greater number of values by making the amplitude of the transmission signal have multiple potential levels. As methods that do not use multiple potential levels, a method of transmitting data using pulse width modulation in which the pulse width is varied at multiple steps has been known (e.g., see Japanese Patent Application Laid-open 2005-79873). Japanese Patent Application Laid-open 2005-79873 discloses a transmission technology by multiplexing the data with different pulse widths over a one clock cycle.
However, the method for reducing the electric power for charging and discharging by using multiple potential levels for the amplitude of the transmission signal, or specifically the method of using multiple potential levels to send the same amount of data as the amount data that is to be transmitted in binary form by a lower number of times of charging/discharging than that during the transmission of the data in binary form, entails the problems that it needs multiple power supplies and that a low-amplitude signal is susceptible to the influence of noise.
On the other hand, when the method of using pulse width-modulated data for transmission, disclosed by Japanese Patent Application Laid-open 2005-79873, is used as inter-chip transmission that entails a power consumption problem when a through-hole interconnection is used, the following problem takes place. FIG. 4 shows a waveforms in a 4-level transmission technique for sending three bits of data via a single interconnection using the pulse width modulation transmitting technique. Here, it is assumed that four kinds of pulse widths are used in a one clock cycle of clock CLK shown in FIG. 4(A). Specifically, the pulse of the shortest width transmits data having a value “0”. The greater the width that the pulse has, the greater is the value of data (data having values “1”, “2” and “3”) that the pulse transmits. Accordingly, the transmission data that is pulse width-modulated as shown in FIG. 4(B) is transmitted in the order of values “1”, “2”, “0” and “3”. This order of data is the same order of data in the digital transmission shown in FIG. 3.
In the example shown in FIG. 4, the number of times of charging/discharging amounts to 2 in total, one charging and one discharging in each clock cycle. In the example shown in FIG. 4, when data is transmitted in an amount that is equal to the amount of data that the digital transmission circuit for transmitting 1-bit (binary) digital data transmits, the number of wires is halved but the number of times of charging/discharging is doubled. Accordingly, in order not to increase the number of times of charging/discharging in the pulse width modulation scheme to be greater than that of the digital transmission circuit, it is necessary to transmit a greater number of values than sixteen values or four bits of data, by a single line. Accordingly, in the transmission circuit based on pulse width modulation, in order not to increase power consumption in excess of that of the aforementioned digital transmission circuit, there is the problem in which a high-speed clock or a high-speed delay control to generate pulses having a pulse width smaller than 1/16 of the clock cycle is needed.